description the cxp87300 is a cmos 8-bit single chip micro- computer of piggyback/evaluator combined type, which is developed for evaluating the function of the cxp87352/87360. features a wide instruction set (213 instructions) which cover various types of data. 16-bit operation/multiplication and division/ boolean bit operation instructions minimum instruction cycle 333ns at 12mhz operation (3.0 to 5.5v) 250ns at 16mhz operation (4.5 to 5.5v) 122 s at 32khz operation applicable eprom lcc type 27c256, lcc type 27c512 (maximum 60kbytes are available.) incorporated ram capacity 2048 bytes peripheral functions ?a/d converter 8-bit, 12-channel, successive approximation method (conversion time of 20 s/16mhz) ?serial interface incorporated buffer ram (auto transfer for 1 to 32 bytes), 1 channel incorporated 8-bit and 8-stage fifo (auto transfer for 1 to 8 bytes), 1 channel ?timer 8-bit timer, 8-bit timer/counter 19-bit time base timer, 32khz timer/counter ?high precision timing pattern generator ppg 19-pin, 32-stage programmable rtg 5 pins, 2 channels ?pwm/da gate output pwm output 12 bits, 2 channels (repetitive frequency 62.5khz/16mhz) da gate pulse output 13 bits, 4channels ?servo input control capstan fg, drum fg/pg, ctl input ?vsync separator ?frc capture unit incorporated 26-bit and 8-stage fifo ?pwm output 14 bits, 1 channel ?viss/vass circuit pulse duty auto detection circuit ?remote control receiving circuit 8-bit pulse measurement counter with on-chip 6-stage fifo ?general purpose prescaler 7 bits (sync1 input frequency division, frc capture possible.) ?hsync counter 12-bit event counter (sync1 input count) interruption 22 factors, 15 vectors, multi-interruption possible standby mode sleep/stop package 100-pin ceramic pqfp note) mask option depends on the type of the cxp87300. refer to the products list for details. structure silicon gate cmos ic ?1 cxp87300 e94x15a68-ps cmos 8-bit single chip microcomputer sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. piggyback/ evaluator type 100 pin pqfp (ceramic) qfp supported lqfp supported
?2 cxp87300 pin assignment in piggyback mode (qfp package) note) 1. nc (pin 90) is always connected to v dd . 2. v ss (pins 41 and 88) are both connected to gnd. 3. mp (pin 39) is always connected to gnd. pb5/ppo13 pb4/ppo12 pb3/ppo11 pb2/ppo10 pb1/ppo9 pb0/ppo8 pc7/rto7 pc6/rto6 pc5/rto5 pc4/rto4 pc3/rto3 pc2/ppo18 pc1/ppo17 pc0/ppo16 pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pi6/so1 pi7/si1 pe0/int0/ckout pe1/ec/int2/hcout pe2/pwm0 pe3/pwm1 pe4/daa0 pe5/daa1 pe6/dab0 pe7/dab1 pg0/cfg pg1/dfg pg2/dpg pg3/pbctl pg4/sync0 pg5/sync1 pg6/exi0 pg7/exi1 an0 an1 an2 an3 pf0/an4 pf1/an5 pf2/an6 pf3/an7 av dd av ref avss pf4/an8 ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 mp rst vss xtal extal cs0 si0 so0 sck0 pf7/an11 pf6/an10 pf5/an9 pb6/ppo14 pb7/ppo15 pa0/ppo0 pa1/ppo1 pa2/ppo2 pa3/ppo3 pa4/ppo4 pa5/ppo5 pa6/ppo6 pa7/ppo7 nc v dd vss tx tex pi1/rmc pi2/pwm pi3/to/ddo/adj pi4/int1/nmi pi5/sck1 a8 a9 a11 nc oe a10 ce d7 d6 a6 a5 a4 a3 a2 a1 a0 nc d0 a7 a12 a15 nc v dd a14 a13 d1 d2 gnd nc d3 d4 d5 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 76 77 78 79 80 81 82 83 84 88 87 86 85 89 90 10 0 99 98 97 96 95 94 91 92 93 49
?3 cxp87300 pin assignment in piggyback mode (lqfp package) note) 1. nc (pin 88) is always connected to v dd . 2. v ss (pins 39 and 86) are both connected to gnd. 3. mp (pin 37) is always connected to gnd. a a pe1/ec/int2/hcout pe2/pwm0 pe3/pwm1 pe4/daa0 pe5/daa1 pe6/dab0 pe7/dab1 pg0/cfg pg1/dfg pg2/dpg pg3/pbctl pg4/sync0 pg5/sync1 pg6/exi0 pg7/exi1 an0 an1 an2 an3 pf0/an4 pf1/an5 pf2/an6 pf3/an7 av dd av ref pb3/ppo11 pb2/ppo10 pb1/ppo9 pb0/ppo8 pc7/rto7 pc6/rto6 pc5/rto5 pc4/rto4 pc3/rto3 pc2/ppo18 pc1/ppo17 pc0/ppo16 pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 mp rst vss xtal extal cs0 si0 so0 sck0 pf7/an11 pf6/an10 pf5/an9 pf4/an8 avss pb4/ppo12 pb5/ppo13 pb6/ppo14 pb7/ppo15 pa0/ppo0 pa1/ppo1 pa2/ppo2 pa3/ppo3 pa4/ppo4 pa5/ppo5 pa6/ppo6 pa7/ppo7 nc v dd vss tx tex pi1/rmc pi2/pwm pi3/to/ddo/adj pi4/int1/nmi pi5/sck1 pi6/so1 pi7/si1 pe0/int0/ckout 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 76 77 78 79 80 81 82 83 84 88 87 86 85 89 90 10 0 99 98 97 96 95 94 91 92 93 2 3 4 5 6 7 8 9 10 11 12 13 14 1 15 16 17 18 19 20 21 22 23 24 25 26 27 28 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 d0 d1 d2 gnd v dd a14 a13 a8 a9 a11 oe a10 ce d7 d6 d5 d4 d3 26 27 28 29 30 33 50 40 39 38 37 36 35 34 31 32 41 42 43 44 45 46 47 48 49
?4 cxp87300 pin assignment in evaluator mode (qfp package) note) 1. nc (pin 90) is always connected to v dd . 2. v ss (pins 41 and 88) are both connected to gnd. 3. mp (pin 39) is always connected to gnd. pb5/ppo13 pb4/ppo12 pb3/ppo11 pb2/ppo10 pb1/ppo9 pb0/ppo8 pc7/rto7 pc6/rto6 pc5/rto5 pc4/rto4 pc3/rto3 pc2/ppo18 pc1/ppo17 pc0/ppo16 pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pi6/so1 pi7/si1 pe0/int0/ckout pe1/ec/int2/hcout pe2/pwm0 pe3/pwm1 pe4/daa0 pe5/daa1 pe6/dab0 pe7/dab1 pg0/cfg pg1/dfg pg2/dpg pg3/pbctl pg4/sync0 pg5/sync1 pg6/exi0 pg7/exi1 an0 an1 an2 an3 pf0/an4 pf1/an5 pf2/an6 pf3/an7 av dd av ref avss pf4/an8 ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 mp rst vss xtal extal cs0 si0 so0 sck0 pf7/an11 pf6/an10 pf5/an9 pb6/ppo14 pb7/ppo15 pa0/ppo0 pa1/ppo1 pa2/ppo2 pa3/ppo3 pa4/ppo4 pa5/ppo5 pa6/ppo6 pa7/ppo7 nc v dd vss tx tex pi1/rmc pi2/pwm pi3/to/ddo/adj pi4/int1/nmi pi5/sck1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 76 77 78 79 80 81 82 83 84 88 87 86 85 89 90 10 0 99 98 97 96 95 94 91 92 93 49 a8 a9 a11 nc halt a10 e/p i/t mon a6/d6 a5/d5 a4/d4 a3/d3 a2/d2 a1/d1 a0/d0 nc rd a7/d7 a12 a15 nc v dd a14 a13 wr sync gnd nc c2 c1 rst 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1
?5 cxp87300 pin assignment in evaluator mode (lqfp package) note) 1. nc (pin 88) is always connected to v dd . 2. v ss (pins 39 and 86) are both connected to gnd. 3. mp (pin 37) is always connected to gnd. a pe1/ec/int2/hcout pe2/pwm0 pe3/pwm1 pe4/daa0 pe5/daa1 pe6/dab0 pe7/dab1 pg0/cfg pg1/dfg pg2/dpg pg3/pbctl pg4/sync0 pg5/sync1 pg6/exi0 pg7/exi1 an0 an1 an2 an3 pf0/an4 pf1/an5 pf2/an6 pf3/an7 av dd av ref pb3/ppo11 pb2/ppo10 pb1/ppo9 pb0/ppo8 pc7/rto7 pc6/rto6 pc5/rto5 pc4/rto4 pc3/rto3 pc2/ppo18 pc1/ppo17 pc0/ppo16 pj7 pj6 pj5 pj4 pj3 pj2 pj1 pj0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 ph7 ph6 ph5 ph4 ph3 ph2 ph1 ph0 mp rst vss xtal extal cs0 si0 so0 sck0 pf7/an11 pf6/an10 pf5/an9 pf4/an8 avss pb4/ppo12 pb5/ppo13 pb6/ppo14 pb7/ppo15 pa0/ppo0 pa1/ppo1 pa2/ppo2 pa3/ppo3 pa4/ppo4 pa5/ppo5 pa6/ppo6 pa7/ppo7 nc v dd vss tx tex pi1/rmc pi2/pwm pi3/to/ddo/adj pi4/int1/nmi pi5/sck1 pi6/so1 pi7/si1 pe0/int0/ckout 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 76 77 78 79 80 81 82 83 84 88 87 86 85 89 90 10 0 99 98 97 96 95 94 91 92 93 26 27 28 29 30 33 50 40 39 38 37 36 35 34 31 32 41 42 43 44 45 46 47 48 49 2 3 4 5 6 7 8 9 10 11 12 13 14 1 15 16 17 18 19 20 21 22 23 24 25 26 27 28 a15 a12 a7/d7 a6/d6 a5/d5 a4/d4 a3/d3 a2/d2 a1/d1 a0/d0 rd wr sync gnd v dd a14 a13 a8 a9 a11 halt a10 e/p i/t mon rst c1 c2
?6 cxp87300 eprom read timing (ta = ?0 to +75?, v dd = 3.0 to 5.5v, vss = 0v) address ? data hold time address ? data input delay time item symbol pin min. max. unit t ih t acc a0 to a15 d0 to d7 a0 to a15 d0 to d7 0 100 * 1 75 * 2 ns ns t acc t ih 0.8v dd 0.8v dd 0.2v dd 0.2v dd input data address data a0 to a15 d0 to d7 products option item ttl schmitt existent cmos schmitt 27c512 1 27c512 1 * 1 on pg4/sync0 pin and pg5/sync1 pin, the input circuit format can be selected to every pin. products list * 1 at 12mhz operation (v dd = 4.5 to 5.5v) * 2 at 12mhz operation (v dd = 3.0 to 5.5v), at 16mhz operation (v dd = 4.5 to 5.5v) piggyback/evaluator product cxp87300-u01q cxp87300-u01r 100-pin ceramic pqfp eprom 60kbytes 27c256 2 mask product 100-pin plastic qfp/lqfp existent/non-existent cmos schmitt/ttl schmitt 52kbytes 60kbytes cxp87360 cxp87352 cmos schmitt cxp87300-u02q cxp87300-u02r CXP87300-U05R package rom capacity pull-up resistor for reset pin input circuit format * 1
?7 cxp87300 pin 1 index pin 1 marking lcc type eprom pin 1 marking piggyback mode piggyback/evaluator product evaluator mode cpu probe note) note) evaluation cap should be connected to cpu probe. eprom adaptor pin 1 marking cpu probe for lqfp pin 1 index u05r used u01r and u02r used for lower address for upper address lcc type eprom for low voltage pin 1 marking (27c256 only) lower address upper address address lower upper memory space eprom (27c256) 1000 h to 7fff h 1000 h to 7fff h 8000 h to ffff h 0000 h to 7fff h (27c512 only) eprom adaptor pin 1 marking piggyback mode/evaluator mode can be switched as shown below.
?8 cxp87300 package outline unit: mm sony code eiaj code jedec code package structure package material lead treatment lead material package weight ceramic gold plating 42 alloy 10.44 max 0.50 0.25 0.15 ?0.02 + 0.05 3.57 0.36 18.7 16.3 0.2 100 81 31 50 80 51 1 30 9.48 11.66 15.58 0.2 24.7 22.3 0.25 6.0 4.5 0.3 1.27 0.13 12.02 14.22 18.12 0.2 pin no. 1 index index pqfp-100c-l01 aqfp100-c-0000-a 100pin pqfp (ceramic) 81 80 51 1 30 100 50 31 0.3 0.08 0.65 0.05 pin no. 1 index 0.7 1.0 1.3 0.3 0.45 5.7g sony code eiaj code jedec code package structure package material lead treatment lead material package weight ceramic gold plating 42 alloy 2.2g pqfp-100c-l02 aqfp100-c-1414-a 100pin pqfp (ceramic) 16.0 0.4 14.0 0.2 12.8 0.2 25 1 51 75 50 26 76 100 index 0.18 ?0.03 + 0.08 0.5 0.05 12.0 0.15 1.5 3.2 0.2 0.2 ?0.13 + 0.15 0.127 ?0.02 + 0.05 3.32 6.9 0.18 ?0.03 + 0.08 0.5 0.05 12.0 0.15 12.4 index 0.8 0.2
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